SOC Verification using System Verilog (Udemy)

SOC Verification using System Verilog (Udemy)
Free Course
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Effort
Certification
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Students of VLSI/Digita/Embedded systems design, Semiconductor engineering professionals.
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SOC Verification using System Verilog (Udemy)
A comprehensive course that teaches System on Chip design verification concepts and coding in System Verilog Language.

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This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in System Verilog language - which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course.





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MOOC List is learner-supported. When you buy through links on our site, we may earn an affiliate commission.

Free Course
Students of VLSI/Digita/Embedded systems design, Semiconductor engineering professionals.

MOOC List is learner-supported. When you buy through links on our site, we may earn an affiliate commission.