Aneesh Nainani




Aneesh Nainani was born in Rajasthan, India. He received his B.Tech and M.Tech degrees in electrical engineering from the Indian Institute of Technology Bombay, India, both in 2007 and the Ph.D. degree in electrical engineering from Stanford University in 2011. He has worked with CEA-LETI, IBM, SEMATECH, and Applied Materials. He is currently a Senior Technologist with Applied Materials in Santa Clara, CA, and also holds a Assistant Professor (Consulting) appointment at Stanford University.

He currently serves on the technical working group at International Technology Roadmap for Semiconductors (ITRS) and on the Technical Advisory Board for Device Sciences at Semiconductor Research Corporation (SRC). He has published more than 50 papers on nanocrystal flash memory, III-V CMOS, and thin-film solar cells.

His research interests are in the physics, technology and economics of semiconductors and nanoscience. More recently he has been tinkering with digital education and content delivery.

Dr. Nainani was a recipient of several awards, including the Intel PhD Fellowship, the School of Engineering Fellowship from Stanford University, and the National Talent Scholarship from the Government of India.

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