Computer Architecture with an Industrial RISC-V Core [RVfpga] (edX)

RISC-V, an open-standard computer architecture, is transforming processor design and software/hardware co-design, including enabling open source hardware implementations. This means that software development can occur alongside hardware development, accelerating the design process. Enroll today to develop your understanding of the RISC-V architecture and its ecosystem and get familiar with the RISC-V cores and system-on-chip.
This course is for junior level or higher university computer science, electrical and computer engineers and other technical students as well as others who would like to learn and experiment with RISC-V.
Upon completion, learners should be able to use RISC-V to improve security, power consumption and performance of processors and help shape the future of computer architecture.

What you'll learn

• Understand and be able to use the RISC-V Computer Architecture
• Develop and compile C and RISC-V Assembly code for the RVfpga SoC
• Understand, use and extend the Input/Output System of the RVfpga SoC
• Understand and configure the microarchitecture of the VeeR EH1 CoreTM and test its different features using - Performance Counters and industry-standard Benchmarks.
• Execute programs on the Nexys A7 board (optional) and simulate programs on different simulation tools: Whisper instruction set simulator (ISS); Verilator-based RVfpga-ViDBo; RVfpga-Pipeline; and RVfpga-Trace.

Prerequisites:
Learners should have a fundamental understanding of the following topics: digital logic design, high-level programming (such as C programming), assembly programming, RISC-V instruction set architecture, processor microarchitecture, and memory and input/output systems.
The software and optional hardware is supported in Linux, and most of it is also supported in Windows and macOS. A Ubuntu 22.04 Virtual Machine is also provided with everything installed on it, so that you can easily use all tools in a Linux environment (independently of the OS that you use in your computer) out-of-the-box. The course may be completed in simulation, so the hardware (the Nexys A7 FPGA board) is optional.

Syllabus

Welcome!
Chapter 1. Installation and Initial Demonstrations
Chapter 2. C Programming with the RVfpga SoC
Chapter 3. RISC-V Assembly Programming with the RVfpga SoC
Chapter 4. RISC-V Function Calls
Chapter 5. Mixing C and Assembly Functions in a Program
Chapter 6. Introduction to Peripherals and Input/Output
Chapter 7. More I/O: 7-Segment Displays
Chapter 8. More I/O: Timers
Chapter 9. Interrupts
Chapter 10. Delving Deeper into the RISC-V VeeR Core
Final Exam (Verified Track only)