Digital design with FPGAs (Coursera)

The FPGAs are extremely powerful to implement computationally demanding algorithms. Gigabits per second broadband signal processing for 5G systems, cryptography, hash generation, radar applications and ASIC prototyping - all the industry areas, where high computational load is present are subjects to apply FPGAs.
In this course you will start from the very basics of digital design and then in parallel (as supposed by the parallel nature of FPGAs) will improve the skills in theory, language (VHDL), IDE features and digital signal processing implementation. The course includes theory and labs on basic combinatorial and sequential logic, examples of various approaches for DSP algorithms implementation, techniques for high speed or low area development, design analysis tools and best coding practices.
In the learning process, you:
— Learn the basic theory of digital devices
— Learn VHDL language for FPGA programming
— Learn how to work with Vivado IDE
— Get practical skills for FPGA programming

What You Will Learn

• Implement digital devices in FPGAs, using Xilinx Vivado IDE and VHDL
• Simulate the behavior of your digital device, using your testbench and Vivado Simulator
• Analyze the implemented device in terms of resources, throughput, latency and maximum clock frequency

Syllabus

WEEK 1
Combinational logic
In this part we consider the basic building blocks for logic functions implementation: various combinational logic. Also we start with VHDL language key syntax constructions and perform 4 labs with Xilinx FPGA Artix7, using Vivado IDE.

WEEK 2
Sequential logic
In this part we introduce basic storage elements, which allow to create sequential logic blocks and finally - any synchronous digital device. We continue learning VHDL syntax constructs. Four labs more appear in this part.

WEEK 3
Fixed-point and floating-point numbers
In this part fixed- and floating-point numbers representation and operations on them are considered. This is important for deeper understanding on what goes with numbers inside FPGA. Two labs and more VHDL syntax constructs appear in this part too.

WEEK 4
FPGA specific
In this part we have deeper view on the processes, which occur incide FPGAs. We consider several advanced topics about static timing analysis, metastability, resetes and overall performance and resource consumption. Finally we summarise with general ideas about development for FPGAs. We also have two final labs here.