Real-Time Mission-Critical Systems Design (Coursera)

This course can also be taken for academic credit as ECEA 5317, part of CU Boulder’s Master of Science in Electrical Engineering degree.

At the end of this course learners will be able to apply an architectural style (cyclic executive, RTOS, or embedded Linux) to more detailed design of a mission critical system, a soft real-time system, or a mixed hard and soft real-time system, including:

- Thorough understanding of hardware/software device interfaces and resource view for hardware abstraction layers (HAL, BSP)

- Design trade-offs with different real-time hardware architectures including single core, multi-core, hybrid-FPGA, GP-GPU, and DSP systems, with emphasis on multi-core

- Mission critical embedded systems architecture and key design elements

- Fault tolerant processing, memory, and I/O concepts

Syllabus

WEEK 1

Device I/O interfaces and Drivers for Real-time Systems

This module covers RTES software to hardware interface using device abstraction and driver interfaces as well as system scaling.

WEEK 2

Fault Tolerant Memory and Storage for Mission Critical Systems

This module covers use of key algorithms such as error correct codes, redundant arrays of devices, and use of flash file systems with persistent memory.

WEEK 3

Solving performance and reliability defects in real-time systems

Service software implementation efficiency and optimization methods are covered so that computations can be completed by deadlines. Methods of profiling and tracing applications as well as the whole system are covered.

WEEK 4

Difference between high availability and high reliability for hard and soft real-time systems

This module integrates fault tolerant and recovery methods with overall strategies for system level fault detection, isolation and recovery. Design with consideration of failure modes and effects analysis is covered along with redundancy management for high availability.