This is an open online course that teaches you how to design a digital ASIC (standard cell or FPGA) using the Verilog Hardware Description Language. At the end of this course you will have an understanding of what ASICs are, and how they are designed and verified and you will have demonstrated those skills via a small project. Anyone can enroll in this course. During the course you will use windows-7 based computer aided design tools that are freely available on the web.
All the course content and automated/peer grading is identical to the regular on-campus version taught by Dr. Paul Franzon at North Carolina State University.
After completing the course successfully with a grade of 80% or better, you will have an opportunity to “upgrade” your achievements to the status of a a regular for-credit course by enrolling as a non-degree studies distance education student at NCSU to complete the human graded and proctored portions not available in the pure online version.
Recommended Readings:
