As founder of Redwood EDA, Steve Hoover is fostering an open-source silicon ecosystem through numerous technologies including the WARP-V CPU core generator with support for RISC-V. His main focus is design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog). He is also the lead developer of the first CLaaS open-source framework for cloud FPGAs. Steve holds a BS in Electrical Engineering Summa Cum Laude from Rensselaer Polytechnic Institute and an MS in Computer Science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel.
EdX
Embark on an exciting journey into hardware creation with 'Building a RISC-V CPU Core'. This course is designed for tech enthusiasts and beginners alike, offering hands-on experience in designing a functional RISC-V CPU core. With no prerequisites required, you'll dive straight into learning digital logic design and microarchitecture using cutting-edge tools.