Leland Chang




Leland Chang received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley and joined the IBM T. J. Watson Research Center in 2003, where he is now Manager of Design and Technology Solutions. His work focuses on power efficiency in high-performance systems – spanning the development of new technology elements, the design of high-performance memory and power management circuits, and the exploration of novel accelerator and memory system architectures. Key contributions have included early demonstration of the FinFET structure for CMOS scaling, 8T-SRAM for voltage scaling in high-performance caches, high-speed register files with double-pumped access ports, and high-efficiency voltage conversion circuits using new passive device technologies. He is the author of 74 technical articles and 84 patents and is currently a member of the ISSCC technical program committee.

More info: http://www.linkedin.com/pub/leland-chang/1/2a4/b02

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Dec 1st 2014

ISSCC Previews: Circuit and System Insights, covering several fields, including wireless and wireline comm., analog, digital, and memory.

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